In a synchronous digital system, such as a computer chip, a clock signal is employed to provide a time of reference for the transmission of data within the system. A system clock produces an electronic-clock signal in the form of a steady high-frequency signal that synchronizes the operation of the system components. A clock signal oscillates between distinctive high and low states. The transitions between high and low states create rising and falling clock edges. A clock cycle is a single complete traversal of the clock signal from a rising clock edge through a falling clock edge until the start of the next rising edge.
Clock signals are distributed to, and are used and needed by every end-of-clock-cycle latch and have other uses in synchronous systems. For example, ideally a clock signal is electronically distributed over a computer chip to all chip components so that all components are operating with a clock edge that is minimally skewed or phase shifted with respect to any other clock edge. Thus, synchronous systems employ clock distribution networks, such as an H-tree network, that are designed to distribute the clock signal from the system clock to all the components that use it.
Since components transmit and process data signals with reference to clock edges, the clock edges must be particularly clean and sharp. However, clock signals are vulnerable to technology scaling. For example, relatively long global interconnect lines become significantly more resistive as line dimensions are decreased. Thus a clock signal can be degraded as the dimensions of the lines used to distribute the clock signal decrease and the clock edges can become less distinct. The clock distribution network also takes a significant fraction of the total power consumed by the synchronous system.
In order to handle the global distribution of clock signals on a chip, there are currently two alternatives. One way to deal with the problem is to latch data signals to the clock signal at intervals that are shorter than the distance the data signal travels in one clock cycle so that the data signal is always kept in time with the clock. Alternatively, data signals can be sent with a forwarded clock which is retimed at each destination by feeding data through an asynchronous first-in, first-out (“FIFO”) device, which is timed at one end by the forwarded clock and at the other end by the destination's clock. However, both of these solutions increase latency of transmission, require extra power, and use a relatively large chip surface area.
Engineers have recognized a need for systems and methods that can compensate for clock skew and provide lower latency and less power consumption than currently available solutions.